The Rise of the Dark RISC-V?

DarkRISCV, an open source RISC-V core for FPGAs

Alasdair Allan
3 min readAug 30, 2018

After nearly a decade of neglect, the last year has seen a big uptick in the adoption of the the RISC-V standard. The arrival of the first commercially-available open source system-on-chip (SoC) based on the architecture — the 32-bit Freedom Everywhere 310 — along with the first Arduino-compatible development board called the HiFive1, from the Bay Area startup SiFive, was seen as a real milestone by the open hardware community.

Which doesn’t mean that keeping other independent implementations of the standard around isn’t still important, which is where DarkRISCV comes in.

The Freedom E310 (FE310) SoC. The very first RISC-V chip. (📷: SiFive)

Written in the dark hours of the night, between the hours of 2 and 8 o’clock in the morning of August 19th by Marcelo Samsoniuk, the DarkRISCV stack is an experimental open source implementation of the RISC-V standard targeting the low-cost Xilinx Spartan-6 family of FPGAs. Following a week of debugging, Samsoniuk has released the implementation to GitHub under a BSD license.

“The general concept is based in my other early RISC processors and composed by a simplified two stage pipeline where a instruction is fetch from a instruction memory in the first clock and then decoded/executed in the second clock. The pipeline is overlapped without interlocks, in a way the darkriscv can reach the performance of one clock per instruction most of time (the exception is after a branch, where the pipeline is flushed and one clock is lost). As addition, the code is very compact, with around two hundred lines of obfuscated but beautiful Verilog code.” Marcelo Samsoniuk

While the DarkRISCV implementation is not as full featured as some other RISC-V implementations, it does implement most of the RISC-V RV32I instruction set and works on real Spartan-6 hardware.

With the first GAP8 processor samples by Open-Silicon shipping, we’re almost in a place where we have multiple vendors producing open silicon built around the RISC-V core, and when that happens we’ll be in a very different place. At that point, we’re in a real open hardware environment because we no longer have vendor lock in, and it’s going to be interesting to see whether that makes a difference to the availability of boards based on RISC-V.

Until then, however, the availability of implementations of the RISC-V architecture, and the ability for people to get hands on with it—whether that’s using an FPGA or not—is important to the ecosystems continued health.

Full details of the DarkRISCV implementation, as well as some interesting notes with indications of not just what, and how, he implemented various parts of the standard, but also why Samsoniuk took certain paths are available in the project’s GitHub repo.

[h/t: Adafruit]