Building Open Hardware With RISC-V Silicon

Traditionally the problem with building “real” open hardware is that it is never really going to be open. While the RISC-V open-source architecture, created by researchers at Berkeley, has been around since 2010 no one had bothered to use it. So eventually, as you worked your way down and reached the silicon it meant that — at least until very recently — your silicon was going to be proprietary. Your hardware was not open.

The Freedom E310 (FE310) SoC. The first RISC-V chip. (📷: SiFive)

Late last year, the Bay Area startup SiFive announced the Freedom Everywhere 310 — the first commercially-available open-source SoC based on the RISC-V architecture. The RTL — the register transfer level — for the cores are freely available on GitHub.

However if you wanted to integrate a RISC-V core into your own chip, things were still a bit problematic. This changed last week when SiFive announced that their Coreplex IP architecture was available for licensing. Their RISC-V core designs can be licensed for a fixed price because, unlike ARM, the company is not intending to charge a per-core licensing fee.

The Coreplex architecture includes the E31 core—a 32-bit processor, intended to replace an ARM Cortex-M3 inside sensors and wearables—and the E51 core, a 64-bit processor designed to serve as a controller in larger chips.

The HiFive-1 Development Board (📷: SiFive)

If you want to pick up your own RISC-V based board and start playing around with it, the HiFive1—open source, and Arduino compatible—is available on Crowd Supply. The board is based around the SiFive FR310 SoC.



Scientist, Author, Hacker, Maker, and Journalist.

Get the Medium app

A button that says 'Download on the App Store', and if clicked it will lead you to the iOS App store
A button that says 'Get it on, Google Play', and if clicked it will lead you to the Google Play store